1 ? fn4125.4 hc-5504b1 itu low cost, pabx slic with 40ma loop feed the intersil slic incorpor ates many of the borsht functions on a single ic chip. this includes dc battery feed, a ring relay driver, supervisory and hybrid functions. this device is designed to maintain transmission performance in the presence of externally induced longitudinal currents. using the unique intersil diel ectric isolation process, the slic can operate directly with a wide range of station battery voltages. the slic also provides selectiv e denial of power. if the pbx system becomes overloaded during an emergency, the slic will provide system protection by denying power to selected subscriber loops. the intersil slic is ideally suited for the design of new digital pbx systems by eliminating bulky hybrid transformers. pinout hc-5504b1 (plcc) top view features ? low cost version of the hc-5504b ? capable of 5v or 12v (v b +) operation ? monolithic integrated device ? di high voltage process ? compatible with worl dwide pbx performance requirements ? controlled supply of battery feed current for short loops (41ma) ? internal ring relay driver ? allows interfacing with negative superimposed ringing systems ? low power consumption during standby ? switch hook ground key and ring trip detection functions ? selective denial of power to subscriber loops applications ? solid state line interface circuit for analog and digital pbx systems ? direct inward dial (did) trunks ? voice messaging pbxs ? related literature - an549, the hc-5502s/4x telephone subscriber line interface circuits (slic) - an571, using ring sync with hc-5502a and hc-5504 slics part number information part number temp. range ( o c) package pkg. dwg. # hc4p5504b1-5 0 to 75 28 ld plcc n28.45 c 3 dg n/c rs rd tf rx +in n/c out c 2 rc ring tip tx ag c 4 -in rf bg n/c shd gkd pd v b + n/c 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 3 rfs v b - data sheet august 2003 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved all other trademarks mentioned are the property of their respective owners. o b s o l e t e p r o d u c t r e c o m m e n d e d r e p l a c e m e n t h c 5 5 0 4 b
2 absolute maxi mum ratings (note 1) thermal information maximum continuous supply voltages (v b -) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -60 to 0.5v (v b +) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 15v (v b + - v b -) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75v relay drive voltage (v rd ). . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 15v operating conditions operating temperature range hc-5504b1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 75 o c relay driver voltage (v rd ) . . . . . . . . . . . . . . . . . . . . . . . . 5v to 12v positive supply voltage (v b +) . . . 4.75v to 5.25v or 10.8v to 13.2v negative supply voltage (v b -) . . . . . . . . . . . . . . . . . . . -42v to -58v high level logic input voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.4v low level logic input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6v loop resistance (r l ) . . . . . . . . . . . . . . . . . . . . . . . .200 ? to 1200 ? thermal resistance (typical, note 2) ja ( o c/w) 28 lead plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 maximum junction temperature plastic . . . . . . . . . . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (plcc - lead tips only) die characteristics transistor count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 diode count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 die dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 x 102 substrate potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . connected process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bipolar-di caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. absolute maximum ratings are limiting values, applied individual ly, beyond which the serviceability of the circuit may be impai red. functional operability under any of these conditi ons is not necessarily implied. 2. ja is measured with the component mount ed on an evaluation pc board in free air. electrical specifications unless otherwise specified, v b - = -48v, v b + = 12v and 5v, ag = bg = dg = 0v, typical parameters t a = 25 o c. min-max parameters are over operating temperature range parameter conditions min typ max units on hook power dissipation i long = 0 (note 2), v b + = 12v - 170 235 mw off hook power dissipation r l = 600 ? , i long = 0 (note 3), v b + = 12v - 425 550 mw off hook i b + r l = 600 ? , i long = 0 (note 3), t a = 25 o c - - 5.3 ma off hook i b - r l = 600 ? , i long = 0 (note 3) - 35 41 ma off hook loop current r l = 1200 ? , i long = 0 (note 3) - 21 - ma off hook loop current r l = 1200 ? , v b - = -42v, i long = 0 (note 3) t a = 25 o c 17.5 - - ma off hook loop current r l = 200 ? , i long = 0 (note 3) 36 41 48 ma fault currents tip to ground - 14 - ma ring to ground - 55 - ma tip to ring - 41 - ma tip and ring to ground - 55 - ma ring relay drive v ol i ol = 62ma - 0.2 0.5 v ring relay driver off leakage v rd = 12v, rc = 1 = high, t a = 25 o c - - 100 a ring trip detection period r l = 600 ? - 2 3 ring cycles switch hook detection threshold shd = v ol 10 - - ma shd = v oh - - 5 ma ground key detection threshold gkd = v ol 20 - - ma gkd = v oh - - 10 ma loop current during power denial r l = 200 ? - 2 - ma dial pulse distortion 0 - 5 ms hc-5504b1
3 receive input impedance (note 4) - 110 - k ? transmit output impedance (note 4) - 10 20 ? 2-wire return loss (referenced to 600 ? + 2.16 f), (note 4) sr l lo - 15.5 - db er l - 24 - db sr l hi - 31 - db longitudinal balance 1v rms 200hz - 3400hz, (note 4) ieee method 0 o c t a 75 o c 2-wire off hook 53 58 - db 2-wire on hook 53 58 - db 4-wire off hook 50 58 - db low frequency longitudinal balance r.e.a. method, (note 4), r l = 600 ? 0 o c t a 75 o c - - 23 dbrnc - - -67 dbm0p insertion loss at 1khz, 0dbm input level, referenced 600 ? 2-wire to 4-wire, 4-wire to 2-wire - 0.05 0.2 db frequency response 200 - 3400hz referenced to absolute loss at 1khz and 0dbm signal level (note 4) - 0.02 0.05 db idle channel noise (note 4) 2-wire to 4-wire, 4-wire to 2-wire - 1 5 dbrnc - -89 -85 dbm0p absolute delay (note 4) 2-wire to 4-wire, 4-wire to 2-wire - - 2 ms trans hybrid loss balance network set up for 600 ? termination at 1khz 30 40 - db overload level v b + = +5v 1.5 - - v peak 2-wire to 4-wire, 4-wire to 2-wire v b + = 12v 1.75 - - v peak level linearity at 1khz, (note 4) referenced to 0dbm level 2-wire to 4-wire, 4-wire to 2-wire +3 to -40dbm - - 0.05 db -40 to -50dbm - - 0.1 db -50 to -55dbm - - 0.3 db power supply rejection ratio (note 4) v b + to 2-wire 30 - 60hz, r l = 600 ? 15 - - db v b + to transmit 15 - - db v b - to 2-wire 15 - - db v b - to transmit 15 - - db v b + to 2-wire 200 - 16khz, r l = 600 ? 30 - - db v b + to transmit 30 - - db v b - to 2-wire 30 - - db v b - to transmit 30 - - db logic input current (rs, rc , pd ) 0v v in 5v - - 100 a electrical specifications unless otherwise specified, v b - = -48v, v b + = 12v and 5v, ag = bg = dg = 0v, typical parameters t a = 25 o c. min-max parameters are over operating temperature range (continued) parameter conditions min typ max units hc-5504b1
4 logic inputs logic ?0? v il - - 0.8 v logic ?1? v ih 2.0 - 5.5 v logic outputs logic ?0? v ol i load 800 a, v b + = 12v, 5v - 0.1 0.5 v logic ?1? v oh i load 80 a, v b + = 12v 2.7 5.0 5.5 v i load 40 a, v b + = 5v 2.7 - 5.0 v electrical specifications unless otherwise specified, v b - = -48v, v b + = 12v and 5v, ag = bg = dg = 0v, typical parameters t a = 25 o c. min-max parameters are over operating temperature range (continued) parameter conditions min typ max units uncommitted op amp specifications parameter conditions min typ max units input offset voltage - 5 - mv input offset current - 10 - na input bias current - 20 - na differential input resistance (note 4) - 1 - m ? output voltage swing r l = 10k, v b + = 12v - 6.2 6.6 v peak r l = 10k, v b + = 5v - 3 - v peak output resistance a vcl = 1 (note 4) - 10 - ? small signal gbw (note 4) - 1 - mhz notes: 3. i long = longitudinal current. 4. these parameters are controlled by design or process parameters and are not directly te sted. these parameters are characterized upon initial design release, upon design changes which woul d affect these characteristics, and at intervals to assure product quality and sp ecification compliance. hc-5504b1
5 pin descriptions 28 pin plcc symbol description 2 tip an analog input connected to the tip (more posit ive) side of the subscriber loop through a 150 ? feed resistor and a ring relay contact. functions with the ring terminal to receive voice signals from the telephone and for loop monitoring purposes. 3 ring an analog input connected to the ring (more negativ e) side of the subscriber loop through a 150 ? feed resistor and a ring relay contact. functions with the tip terminal to receive voice signals from the telephone and for loop monitoring purposes. 4 rfs senses ring side of loop for ground key and ring trip detection. during ringing, the ring signal is inserted into the line at this node and rf is isolated from rfs via a relay. 5 v b + positive voltage source - most positive supply. v b + is typically 12v or 5v. 6 c 3 capacitor #3 - an external capacitor to be connected be tween this terminal and analog ground. required for proper operation of the loop current limiting function, and for filtering v b -. typical value is 0.3 f, 30v. 7 dg digital ground - to be connected to zero potential and serves as a reference for all digital inputs and outputs on the slic microcircuit. 9 rs ring synchronization input - a ttl - compatible clock input . the clock should be arranged such that a positive pulse transition occurs on the zero crossing of the ring voltage sour ce, as it appears at the rfs terminal. for tip side injected systems, the rs pulse should occur on the negative going zero crossing and for ring inject ed systems, on the positive going zero crossing. this ensures that the ring relay ac tivates and deactivates when the instantaneous ring voltage is near zero. if synchronization is not required, the pin should be tied to 5v. 10 rd relay driver - a low active open collector logic out put. when enabled, the external ring relay is energized. 11 tf tip feed - a low impedance analog output connected to the tip terminal through a 150 ? feed resistor. functions with the rf terminal to provide loop current, feed voice signals to the telephone set, and sink longitudinal current. 12 rf ring feed - a low impedance analog output connec ted to the ring terminal through a 150 ? feed resistor. functions with the tf terminal to provide loop current, feed voice signals to the telephone set, and sink longitudinal current. 13 v b - negative voltage source - most negative supply. v b - is typically -48v with an oper ational range of -42v to -58v. frequently referred to as ?battery?. 14 bg battery ground - to be connected to zero potential. all loop current and some quiescent current flows into this ground terminal. 16 shd switch hook detection - a low active ls ttl-compatible logic output. this output is ena bled for loop currents exceeding 10ma and disabled for loop currents less than 5ma. 17 gkd ground key detection - a low active ls ttl-compatible logic ou tput. this output is enabled if the dc current into the ring lead exceeds the dc current out of the tip lead by more than 20ma, and disabled if this cu rrent difference is less than 10ma. 18 pd power denial - a low active ttl - compatible logic input. when enabled, the switch hook detect ( shd ) and ground key detect ( gkd ) are not necessarily valid, and the relay driver ( rd ) output is disabled. 19 rc ring command - a low active ttl - compatible logic input. when enabled, the relay driver ( rd ) output goes low on the next high level of the ring sync (rs) input, as long as the slic is not in the power denial state ( pd = 0) or the subscriber is not already off- hook ( shd = 0). 20 c 2 capacitor #2 - an external capacitor to be connected between th is terminal and digital grou nd. prevents false ground key indications from occurri ng during ring trip detection. typical value is 0.15 f, 10v. this capacitor is not used if ground key function is not required and (pin 17) ma y be left open or connected to digital ground. 21 out the analog output of the spare operational ampl ifier. the output voltage swing is typically 5v. 23 -in the inverting analog input of the spare operational amplifier. 24 +in the non-inverting analog input of the spare operational amplifier. 25 rx receive input, four wire side - a high impedance analog input wh ich is internally bi ased. capacitive coupling to this input is required. ac signals appearing at this input differentially drive the tip feed and ring feed terminals, which in turn drive tip and ring through 300 ? of feed resistance on each side of the line. hc-5504b1
6 functional diagram 26 c 4 capacitor #4 - an external capacitor to be connected bet ween this terminal and analog ground. this capacitor prevents false ground key indication and false ring trip detection from occurring when longitudinal currents are induced onto the subscriber loop from near by power lines and other noise sources. this capacitor is also required for the proper operation of ring trip detection. typical value is 0.5 f, to 1.0 f, 20v. this capacitor should be nonpolarized. 27 ag analog ground - to be connected to zero potential and serves as a reference for the transmit output (tx) and receive input (rx) terminals. 28 tx transmit output, four wire side - a lo w impedance analog output which represen ts the differential voltage across tip and ring. transhybrid balancing must be performed (using the slic microcircuit?s spare op amp) beyond this output to completely implement two to four wire conversion. this output is unbalanced and referenced to analog ground. since the dc level of this output varies with loop curren t, capacitive coupling to the next stage is essential. 1, 8, 15, 22 nc no internal connection. note: all grounds (ag, bg, and dg) must be applied before v b + or v b -. failure to do so may result in premature failure of the part. if a user wishes to run separate grounds off a line card, the ag must be applied first. pin descriptions (continued) 28 pin plcc symbol description + diff amp + op amp loop monitoring ring control 2-wire loop secondary protection line drivers tip ring v b - v b - pd power denial 150 ? ring 150 ? rf bg 150 ? tf tip rd rc rs ring sync ring command ring trip shd gkd tx transmit output out +in -in rx receive input slic microcircuit 1/2 ring relay v b - ring voltage rfs 1/2 ring relay 150 ? switch hook detection ground key detection -1 +1 battery feed loop current limiter hc-5504b1
7 schematic slic functional schematic dip/soic pin numbers shown v b2 v b1 v b2 v b3 v b4 v b5 5v i b1 i b2 i b3 i b4 i b5 i b6 i b7 i b8 v bat i b9 i b10 i b11 v b + v b + a-100 transv?l i/v amp - + i b6 r 6 r 5 r 11 v b + r 7 r 8 r 10 r 9 r 22 r 23 r 3 r 4 r 1 r 2 r 16 r 15 v bat v bat r 12 v bat v b + a-200 long?l i/v amp i b7 - + r 20 v bat v b + a-400 tip feed amp i b4 - + ring feed sense v bat v bat 5v v b4 i b8 ring trip detector + switch hook v b1 i b6 + r 18 detector v b + q d28 q d27 v bat - + - gnd shorts current limiting i b1 v b3 thermal limiting v b5 sttl and logic interface rfc sh gk v b5 - + i b2 load current limiting r 14 r 13 v bat v bat/2 reference r 21 v bat a-300 ring feed amp i b5 - + ring rf tip tf 10 2 3 1 9 rx c 4 v bat bat ana dig v b + gnd gnd gnd 21 22 11 12 23 6 4 + - out 20 19 18 a-500 op amp v bat i b3 v b + v b + 5v i b10 v bat pd 15 rc shd gkd c 2 16 13 17 14 tx c 3 rs rd 8 7 24 5 r 17 v b2 v b + r 19 v bat q d3 q d36 voltage and current bias network hc-5504b1
8 overvoltage protection and longitudinal current protection the slic device, in conjunction with an external protection bridge, will withstand high voltage lightning surges and power line crosses. high voltage surge conditions are as specified in table 1. the slic will withstand longitudinal currents up to a maximum or 30ma rms , 15ma rms per leg, without any performance degradation. logic gate schematic schematic (continued) 15 5 6 12 4 16 13 a b c c b a ttl to sttl ttl to sttl ttl to sttl to r 21 gkd shd rd pd rc rs c 2 ttl to sttl ttl to sttl delay logic bias relay driver sh gk 11 14 3 9 7 8 10 2 1 schottky logic table 1. parameter test condition performance (max) units longitudinal surge 10 s rise/ 1000 s fall 1000 (plastic) v peak metallic surge 10 s rise/ 1000 s fall 1000 (plastic) v peak t/gnd r/gnd 10 s rise/ 1000 s fall 1000 (plastic) v peak 50/60hz current t/gnd r/gnd 11 cycles limited to 10a rms 700 (plastic) v rms hc-5504b1
9 applications diagram figure 1. typical line circuit application with the monolithic slic typical component values c 2 = 0.15 f, 10v. c 3 = 0.3 f, 30v. c 4 = 0.5 f to 1.0 f, 10%, 20v (should be nonpolarized). c 5 = 0.5 f, 20v. c 6 = c 7 = 0.5 f (10% match required) (note 6). c 8 = 0.01 f, 100v. c 9 = 0.01 f, 20v, 20%. r 1 = r 2 = r 3 = 100k ? (0.1% match required, 1% absolute value) z b = 0 for 600 ? terminations (note 6). r b1 = r b2 = r b3 = r b4 = 150 ? (0.1% match required, 1% absolute value). r s1 = r s2 = 1k ? , typically. c s1 = c s2 = 0.1 f, 200v typically, depending on v ring and line length. z 1 = 150v to 200v transient protection. ptc used as ring generator ballast. notes: 5. secondary protection diode bridge recommended is a 2a, 200v type. 6. to obtain the specified transhybrid loss it is necessary for the thr ee legs of the balance network, c 6 -r 1 and r 2 and c 7 -z b -r 3 , to match in impedance to within 0.3%. thus, if c 6 and c 7 are 1 f each, a 20% match is adequate. it should be noted that the transmit output to c 6 sees a -22v step when the loop is closed. too large a value for c 6 may produce an excessively long transient at the op amp output to the pcm filter/codec. 7. a 0.5 f and 100k ? gives a time constant of 50ms. the uncommitted op amp output is internally clamped to stay within 6.6v and is current limited. 8. all grounds (ag, bg, and dg) must be applied before v b + or v b -. failure to do so may result in premat ure failure of the part. if a user wishes to run separate grounds off a line card, the ag must be applied first. 9. application shows ring injected ringing, balanc ed or tip injected configuration may be used. r b4 k 1b k 1a ring ring feed ring feed sense tip v b - slic hc-5504b1 r s1 r b2 r b1 ptc z 1 -48v 150v peak (max) ring generator ring r b3 r s2 c s2 subscriber loop -48v system controller k 1 8 1 9 10 3 2 tip feed tip rd op amp rx tx +in -in out c2 c3 c4 neg. batt. batt. gnd. dig. gnd. ana. gnd. v b + power denial switch hook detect ground key detect ring sync ring cmd 15 13 14 7 16 11 12 6 23 c 9 4 v b + c 8 c 4 c 3 c 2 + + 21 24 20 19 18 17 5 22 c 6 r 1 r 2 c 7 c 5 r 3 balance network pcm filter/ codec switching network z b 5v to 12v primary protec- tion c s1 (note 5) pin numbers given fo r dip/soic package. hc-5504b1
10 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com hc-5504b1 plastic leaded chip carrier packages (plcc) notes: 1. controlling dimension: inch. c onverted millimeter dimensions are not necessarily exact. 2. dimensions and tolerancing per ansi y14.5m-1982. 3. dimensions d1 and e1 do not include mold protrusions. allowable mold protrusion is 0.010 inch (0.25mm) per side. dimensions d1 and e1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. to be measured at seating plane contact point. 5. centerline to be determined where center leads exit plastic body. 6. ?n? is the number of terminal positions. -c- a1 a seating plane 0.020 (0.51) min view ?a? d2/e2 0.025 (0.64) 0.045 (1.14) r 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) tp e e1 0.042 (1.07) 0.048 (1.22) pin (1) identifier c l d1 d 0.020 (0.51) max 3 plcs 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) min 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) min view ?a? typ. 0.004 (0.10) c -c- d2/e2 c l n28.45 (jedec ms-018ab issue a) 28 lead plastic leaded chip carrier package symbol inches millimeters notes min max min max a 0.165 0.180 4.20 4.57 - a1 0.090 0.120 2.29 3.04 - d 0.485 0.495 12.32 12.57 - d1 0.450 0.456 11.43 11.58 3 d2 0.191 0.219 4.86 5.56 4, 5 e 0.485 0.495 12.32 12.57 - e1 0.450 0.456 11.43 11.58 3 e2 0.191 0.219 4.86 5.56 4, 5 n28 286 rev. 2 11/97
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